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1 ltc1091/LTC1092 ltc1093/ltc1094 1-, 2-, 6- and 8-channel, 10-bit serial i/o data acquisition systems n programmable features C unipolar/bipolar conversions C differential/single-ended multiplexer configurations n sample-and-holds n single supply 5v, 10v or 5v operation n direct 3- or 4-wire interface to most mpu serial ports and all mpu parallel i/o ports n analog inputs common mode to supply rails n resolution: 10 bits n total unadjusted error (a grade): 1lsb over temp n fast conversion time: 20 m s n low supply current ltc1091: 3.5ma max, 1.5ma typ LTC1092/ltc1093/ltc1094: 2.5ma max, 1ma typ 5v analog input #1 0v to 5v range analog input #2 0v to 5v range clk d out d in cs ch0 ch1 gnd ltc1091 mpu (e.g., 8051) p1.4 p1.3 p1.2 1091 ta01 8 7 6 5 1 2 3 4 serial data link for 8051 code see applications information section v cc (v ref ) 4.7 f reference voltage (v) 0 linearity error (lsb = ?v ref ) 1.25 1.00 0.75 0.50 0.25 0 4 1091 ta02 1 2 3 5 1 1024 v cc = 5v the ltc ? 1091/LTC1092/ltc1093/ltc1094 10-bit data acquisition systems are designed to provide complete function, excellent accuracy and ease of use when digitiz- ing analog data from a wide variety of signal sources and transducers. built around a 10-bit, switched capacitor, successive approximation a/d core, these devices include software configurable analog multiplexers and bipolar and unipolar conversion modes as well as on-chip sample- and-holds. on-chip serial ports allow efficient data trans- fer to a wide range of microprocessors and microcontrol- lers. these circuits can provide a complete data acquisi- tion system in ratiometric applications or can be used with an external reference in others. the high impedance analog inputs and the ability to operate with reduced spans (below 1v full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. an efficient serial port communicates without external hardware to most mpu serial ports and all mpu parallel i/o ports allowing eight channels of data to be transmitted over as few as three wires. this, coupled with low power consumption, makes remote location possible and facili- tates transmitting data through isolation barriers. temperature drift of offset, linearity and full-scale error are all extremely low (1ppm/ c typically) allowing all grades to be specified with offset and linearity errors of 0.5lsb maximum over temperature. in addition, the a grade devices are specified with full-scale error and total unadjusted error (including the effects of offset, linearity and full-scale errors) of 1lsb maximum over tempera- ture. the lower grade has a full-scale specification of 2lsb for applications where full scale is adjustable or less critical. , ltc and lt are registered trademarks of linear technology corporation. features descriptio u typical applicatio n u
2 ltc1091/LTC1092 ltc1093/ltc1094 wu u package / o rder i for atio order part number order part number ltc1091acn8 ltc1091cn8 1 2 3 4 8 7 6 5 top view cs +in ?n gnd v cc clk d out v ref n8 package 8-lead pdip t jmax = 110 c, q ja = 150 c/w (n) LTC1092acn8 LTC1092cn8 1 2 3 4 8 7 6 5 top view cs ch0 ch1 gnd v cc (v ref ) clk d out d in n8 package 8-lead pdip t jmax = 110 c, q ja = 150 c/w (n) ltc1093acn ltc1093cn ltc1093csw 1 2 3 4 5 6 7 8 9 10 top view n package 20-lead pdip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v ltc1094acn ltc1094cn reduced span conversion modes capability 5v part number #channels unipolar bipolar (separate v ref ) capability ltc1091 2 l pin-for-pin 10-bit upgrade of adc0832 LTC1092 1 ll pin-for-pin 10-bit upgrade of adc0831 ltc1093 6 ll l l ltc1094 8 ll l l product guide t jmax = 110 c, q ja = 150 c/w (n) t jmax = 110 c, q ja = 130 c/w (sw) 1 2 3 4 5 6 7 8 top view sw package 16-lead plastic so wide n package 16-lead pdip 16 15 14 13 12 11 10 9 ch0 ch1 ch2 ch3 ch4 ch5 com dgnd v cc clk cs d out d in v ref agnd v t jmax = 110 c, q ja = 150 c/w (n) supply voltage (v cc ) to gnd or v C ........................ 12v negative supply voltage (v C ) .................... C 6v to gnd voltage analog reference and ltc1091/2 cs inputs ................................. (v C ) C 0.3v to (v cc + 0.3v) digital inputs (except ltc1091/2 cs) .. C 0.3v to 12v digital outputs ........................ C 0.3v to (v cc + 0.3v) a u g w a w u w a r b s o lu t exi t i s power dissipation ............................................. 500mw operating temperature range ltc1091/2/3/4ac, ltc1091/2/3/4c..... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec.)................ 300 c (notes 1, 2) consult factory for industrial and military grade parts.
3 ltc1091/LTC1092 ltc1093/ltc1094 co n verter a n d m ultiplexer characteristics u w u ltc1091a/LTC1092a ltc1091/LTC1092 ltc1093a/ltc1094a ltc1093/ltc1094 parameter conditions min typ max min typ max units offset error (note 4) l 0.5 0.5 lsb linearity error (notes 4, 5) l 0.5 0.5 lsb full-scale error (note 4) l 1.0 2.0 lsb total unadjusted error v ref = 5.000v (notes 4, 6) l 1.0 lsb reference input resistance LTC1092/ltc1093/ltc1094 l 510 510 k w v ref = 5v analog and ref input range (note 7) (v C ) C 0.05v to v cc + 0.05v v on-channel leakage current on-channel = 5v l 11 m a (note 8) off-channel = 0v on-channel = 0v l C1 C1 m a off-channel = 5v off-channel leakage current on-channel = 5v l C1 C1 m a (note 8) off-channel = 0v on-channel = 0v l 11 m a off-channel = 5v the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 3) reco e ded operati g co ditio s u u u uw w ltc1091a/LTC1092a/ltc1093a/ltc1094a ltc1091/LTC1092/ltc1093/ltc1094 symbol parameter conditions min max units v cc supply voltage 4.5 10 v v C negative supply voltage ltc1093/ltc1094, v cc = 5v C 5.5 0 v f clk clock frequency v cc = 5v 0.01 0.5 mhz t cyc total cycle time ltc1091 15 clk cycles + 2 m s LTC1092 12 clk cycles + 2 m s ltc1093/ltc1094 18 clk cycles + 2 m s t hdi hold time, d in alter sclk - v cc = 5v 150 ns t sucs setup time cs before clk - v cc = 5v 1 m s t sudi setup time d in stable before clk - v cc = 5v 400 ns t whclk clk high time v cc = 5v 0.8 m s t wlclk clk low time v cc = 5v 1 m s t whcs cs high time between data transfer cycles v cc = 5v 2 m s t wlcs cs low time during data transfer ltc1091 15 clk cycles LTC1092 12 clk cycles ltc1093/ltc1094 18 clk cycles
4 ltc1091/LTC1092 ltc1093/ltc1094 ac characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 3) ltc1091a/LTC1092a/ltc1093a/ltc1094a ltc1091/LTC1092/ltc1093/ltc1094 symbol parameter conditions min typ max units t smpl analog input sample time see operating sequence 1.5 clk cycles t conv conversion time see operating sequence 10 clk cycles t ddo delay time, clk to d out data valid see test circuits l 400 850 ns t dis delay time, cs - to d out hi-z see test circuits l 180 450 ns t en delay time, clk to d out enabled see test circuits l 160 450 ns t hdo time output data remains valid after sclk 150 ns t f d out fall time see test circuits l 90 300 ns t r d out rise time see test circuits l 60 300 ns c in input capacitance analog inputs on-channel 65 pf analog inputs off-channel 5 pf digital inputs 5 pf the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 3) e lectr ic al c c hara ter st ics digital a d u i dc ltc1091a/LTC1092a/ltc1093a/ltc1094a ltc1091/LTC1092/ltc1093/ltc1094 symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v, i out = 10 m a 4.7 v v cc = 4.75v, i out = 360 m a l 2.4 4.0 v v ol low level output voltage v cc = 4.75v, i out = 1.6ma l 0.4 v i oz hi-z output leakage v out = v cc , cs high l 3 m a v out = 0v, cs high l C3 m a i source output source current v out = 0v C10 ma i sink output sink current v out = v cc 10 ma i cc positive supply current ltc1091, cs high l 1.5 3.5 ma LTC1092/ltc1093/ltc1094, cs high, ref + open l 1.0 2.5 ma i ref reference current LTC1092/ltc1093/ltc1094, v ref = 5v l 0.5 1.0 ma i C negative supply current ltc1093/ltc1094, cs high, v C = C 5v l 150 m a note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, agnd, gnd and ref C wired together (unless otherwise noted). ref C is internally connected to the agnd pin on the ltc1093. dgnd, agnd, ref C and v C are internally connected to the gnd pin on the ltc1091/LTC1092. note 3: v cc = 5v, v ref + = 5v, v ref C = 0v, v C = 0v for unipolar mode and C 5v for bipolar mode, clk = 0.5mhz unless otherwise specified. note 4: these specs apply for both unipolar (ltc1091/LTC1092/ltc1093/ ltc1094) and bipolar (ltc1093/ltc1094 only) modes. in bipolar mode, one lsb is equal to the bipolar input span (2v ref ) divided by 1024. for example, when v ref = 5v, 1lsb (bipolar) = 2(5v)/1024 = 9.77mv. note 5: linearity error is specified between the actual end points of the a/d transfer curve. note 6: total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below v C or one diode drop above v cc . be careful during testing at low v cc levels (4.5v), as high level reference or analog inputs (5v) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. note 8: channel leakage current is measured after the channel selection.
5 ltc1091/LTC1092 ltc1093/ltc1094 change in full-scale error vs temperature ambient temperature ( c) ?0 magnitude of offset change (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 50 1091/2/3/4 g01 ?5 0 25 75 125 100 v cc (v ref ) = 5v f clk = 500khz change in offset error vs temperature ambient temperature ( c) ?0 magnitude of full-scale change (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 50 1091/2/3/4 g03 ?5 0 25 75 125 100 v cc (v ref ) = 5v f clk = 500khz ambient temperature ( c) ?0 magnitude of linearity change (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 50 1091/2/3/4 g02 ?5 0 25 75 125 100 v cc (v ref ) = 5v f clk = 500khz change in linearity error vs temperature ambient temperature ( c) ?0 d out delay time from sclk (ns) 600 500 400 300 200 100 0 50 1091/2/3/4 g05 ?5 0 25 75 125 100 v cc = 5v msb-first data lsb-first data digital input logic threshold vs supply voltage d out delay time vs temperature d out delay time vs supply voltage supply voltage (v) 4 5 678 1091/2/3/4 g06 910 t a = 25 c d out delay time from sclk (ns) 600 500 400 300 200 100 0 msb-first data lsb-first data supply voltage (v) 4 logic threshold (v) 4 3 2 1 0 5 678 1091/2/3/4 g04 910 t a = 25 c maximum clock rate vs temperature ambient temperature ( c) ?0 maximum clk frequency* (mhz) 3.0 2.5 2.0 1.5 1.0 0.5 0 50 1091/2/3/4 g07 ?5 0 25 75 125 100 v cc = 5v maximum clock rate vs supply voltage ambient temperature ( c) ?0 minimum clk frequency** (mhz) 0.3 0.25 0.20 0.15 0.10 0.05 0 50 1091/2/3/4 g09 ?5 0 25 75 125 100 v cc = 5v minimum clock rate vs temperature supply voltage (v) 4 5 678 1091/2/3/4 g08 910 t a = 25 c maximum clk frequency* (mhz) 3.0 2.5 2.0 1.5 1.0 0.5 0 *maximum clk frequency represents the highest frequency at which clk can be operated (with 50% duty cycle) while still providing 100ns setup time for the device receiving the d out data. **as the clk frequency is decreased from 500khz, minimum clk frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 500khz value is first detected. cc hara terist ics uw a t y p i ca lper f o r c e
6 ltc1091/LTC1092 ltc1093/ltc1094 cc hara terist ics uw a t y p i ca lper f o r c e ltc1091/LTC1092/ltc1093/ltc1094 maximum clock rate vs source resistance ltc1091/LTC1092/ltc1093/ltc1094 maximum filter resistor vs cycle time ltc1091/LTC1092/ltc1093/ltc1094 sample-and-hold acquisition time vs source resistance r source ( w ) 10 maximum clk frequency ? (mhz) 1.25 1.00 0.75 0.50 0.25 0 100 1k 10k 1091/2/3/4 g10 v cc = 5v t a = 25 c ??or input v in r source cycle time ( s) 100 maximum r filter ?? ( w ) 1k 10k 100k 10 1000 10000 1091/2/3/4 g11 10 100 + v in c filter 3 1 f r filter r source + ( ) 100 1k 10k 1091/2/3/4 g12 0.1 s & h acquisition time to 0.1% ( s) 1 10 + v in r source + v cc = 5v t a = 25 c 0v to 5v input step ltc1091 change in full-scale error vs supply voltage ambient temperature ( c) ?0 input channel leakage current (na) 100 80 60 40 20 0 50 1091/2/3/4 g13 ?5 0 25 75 125 100 on-channel or off-channel supply voltage (v) 4 offset error [lsb = ?v cc ( v ref )] 1.25 1.00 0.75 0.5 0.25 0 5 678 1091/2/3/4 g14 910 f clk = 500khz t a = 25 c v os = 0.85mv at v cc (v ref ) = 5v 1 1024 supply voltage (v) 4 linearity error [lsb = ?v cc ( v ref )] 1.25 1.00 0.75 0.5 0.25 0 5 678 1091/2/3/4 g15 910 f clk = 500khz t a = 25 c 1 1024 ltc1091/LTC1092 input channel leakage current vs temperature ltc1091 offset error vs supply voltage ltc1091 linearity error vs supply voltage supply voltage (v) 4 change in full-scale error [lsb = ?v cc ( v ref )] 0.50 0.25 0 0.25 0.50 0.75 5 678 1091/2/3/4 g16 910 f clk = 500khz t a = 25 c 1 1024 ambient temperature ( c) ?0 supply current (ma) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 50 1091/2/3/4 g18 ?5 0 25 75 125 100 f clk = 500khz v cc (v ref ) = 5v cs = 5v ltc1091 supply current vs temperature ? as the clk frequency and source resistance are increased, maximum clk frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 500khz, 0 w value is first detected. ?? maximum r filter represents the filter resistor value at which a 0.1lsb change in full-scale error from its value at r filter = 0 is first detected. supply voltage (v) supply current (ma) 7 6 5 4 3 2 1 0 1092/2/3/4 g17 4 5 678910 f clk = 500khz cs = v cc (v ref ) t a = 25 c ltc1091 supply current vs supply voltage
7 ltc1091/LTC1092 ltc1093/ltc1094 cc hara terist ics uw a t y p i ca lper f o r c e LTC1092/ltc1093/ltc1094 unadjusted offset error vs reference voltage LTC1092/ltc1093/ltc1094 linearity error vs reference voltage reference voltage (v) 0 linearity error (lsb = ?v ref ) 1.25 1.00 0.75 0.50 0.25 0 4 1092/2/3/4 g20 1 2 3 5 1 1024 v cc = 5v reference voltage (v) 0 change in full-scale error (lsb = ?v ref ) 1.25 1.00 0.75 0.50 0.25 0 4 1092/2/3/4 g21 1 2 3 5 1 1024 v cc = 5v reference voltage (v) 0.1 0.2 1 5 10 1091/2/3/4 g19 10 9 8 7 6 5 4 3 2 1 0 v cc = 5v v os = 1mv v os = 0.5mv offset error (lsb = ?v ref ) 1 1024 LTC1092/ltc1093/ltc1094 change in full-scale error vs reference voltage supply voltage (v) 4 offset error (lsb) 1.25 1.00 0.75 0.50 0.25 0 5 678 1091/2/3/4 g23 910 v ref = 4v f clk = 500khz v os = 1.25mv at v cc = 5v reference voltage (v) 0.1 0.2 1 5 10 1091/2/3/4 g22 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 noise = 200 v p-p peak-to-peak noise error (lsb) supply voltage (v) 4 linearity error (lsb) 1.25 1.00 0.75 0.50 0.25 0 5 678 1091/2/3/4 g24 910 v ref = 4v f clk = 500khz LTC1092/ltc1093/ltc1094 linearity error vs supply voltage LTC1092/ltc1093/ltc1094 offset error vs supply voltage LTC1092/ltc1093/ltc1094 noise error vs reference voltage LTC1092/ltc1093/ltc1094 change in full-scale error vs supply voltage supply voltage (v) 4 change in full-scale error (lsb) 0.50 0.25 0 0.25 0.50 0.75 5 678 1091/2/3/4 g25 910 v ref = 4v f clk = 500khz supply voltage (v) 4 5 678 1091/2/3/4 g26 910 supply current (ma) 6 5 4 3 2 1 0 v ref open f clk = 500khz cs = v cc t a = 25 c ambient temperature ( c) ?0 supply current (ma) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 50 1091/2/3/4 g27 ?5 0 25 75 125 100 v ref open f clk = 500khz cs = 5v v cc = 5v LTC1092/ltc1093/ltc1094 supply current vs supply voltage LTC1092/ltc1093/ltc1094 supply current vs temperature
8 ltc1091/LTC1092 ltc1093/ltc1094 LTC1092/ltc1093/ltc1094 reference current vs temperature ambient temperature ( c) ?0 reference current (ma) 0.6 0.5 0.4 0.3 0.2 0.1 0 50 1091/2/3/4 g28 ?5 0 25 75 125 100 v ref = 5v ambient temperature ( c) ?0 0 input channel leakage current (na) 100 300 400 500 1000 700 0 25 50 125 1091/2/3/4 g29 200 800 900 600 ?5 75 100 on-channel off-channel guaranteed ltc1093/ltc1094 input channel leakage current vs temperature pi fu ctio s u uu ltc1091/LTC1092 cs (pin 1): chip select input. a logic low on this input enables the ltc1091/LTC1092. ch0, ch1/+ in, C in (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. d in (pin 5)(ltc1091): digital data input. the multiplexer address is shifted into this input. v ref (pin 5)(LTC1092): reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to agnd. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer. v cc (v ref )(pin 8)(ltc1091): positive supply and refer- ence voltage. this pin provides power and defines the span of the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane. v cc (pin 8 )(LTC1092): positive supply voltage. this pin provides power to the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane. ltc1093/ltc1094 ch0 to ch5/ch0 to ch7 (pins 1 to 6/pins 1 to 8): analog inputs. the analog inputs must be free of noise with respect to agnd. com (pin 7/pin 9): common. the common pin defines the zero reference point for all single-ended inputs. it must be free of noise and is usually tied to the analog ground plane. dgnd (pin 8/pin 10): digital ground. this is the ground for the internal logic. tie to the ground plane. v C (pin 9/pin 11): negative supply. tie v C to most negative potential in the circuit. (ground in single supply applications.) agnd (pin 10/pin 12): analog ground. agnd should be tied directly to the analog ground plane. cc hara terist ics uw a t y p i ca lper f o r c e
9 ltc1091/LTC1092 ltc1093/ltc1094 input shift register sample- and-hold 10-bit capacitive dac av cc analog input mux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com d out clk control and timing cs 1091/2/3/4 bd ref + dgnd agnd v ref comp output shift register d in 10-bit sar 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dv cc 19 17 16 18 15 20 (pin numbers refer to ltc1094) block diagra w v ref (pin 11)(ltc1093): reference input. the reference input must be kept free of noise with respect to agnd. ref + , ref C (pins 13, 14 )(ltc1094): reference input. the reference input must be kept free of noise with respect to agnd. d in (pin 12/pin 15): data input. the a/d configuration word is shifted into this input. d out (pin 13/pin 16): digital data output. the a/d con- version result is shifted out of this output. cs (pin 14/pin 17): chip select input. a logic low on this input enables the ltc1093/ltc1094. pi fu ctio s u uu clk (pin 15/pin 18): shift clock. this clock synchronizes the serial data transfer. v cc (pin 16)(ltc1093): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. av cc , dv cc (pins 19, 20)(ltc1094): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. av cc and dv cc should be tied together on the ltc1094.
10 ltc1091/LTC1092 ltc1093/ltc1094 on- and off-channel leakage current load circuit for t ddo , t r , t f 5v i off i on polarity off- channels on-channel 1091/2/3/4 tc01 a a d out 1.4v 3k 100pf test point 1091/2/3/4 tc02 clk d out 0.8v t ddo 0.4v 2.4v 1091/2/3/4 tc03 voltage waveforms for d out delay time, t ddo d out 0.4v 2.4v t r t f 1091/2/3/4 tc04 voltage waveforms for t dis d out waveform 1 (see note 1) 2.0v t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 1091/2/3/4 tc06 voltage waveforms for d out rise and fall times, t r , t f voltage waveforms for t en 1 2 34 ltc1091 d in clk d out start t en b9 0.4v 1091/2/3/4 tc07 cs d out 3k 100pf test point 5v t dis waveform 2, t en t dis waveform 1 1091/2/3/4 tc05 load circuit for t dis , t en test circuits
11 ltc1091/LTC1092 ltc1093/ltc1094 test circuits voltage waveforms for t en 1 LTC1092 clk d out t en b9 0.4v 1091/2/3/4 tc08 cs cs b9 d out t en 0.4v clk ltc1093/ltc1094 1091/2/3/4 tc09 start 7 4 56 3 2 1 d in u s a o pp l ic at i wu u i for atio the ltc1091/LTC1092/ltc1093/ltc1094 are data acquisiton components that contain the following func- tional blocks: 1. 10-bit successive approximation a/d converter 2. analog multiplexer (mux) 3. sample-and-hold (s/h) 4. synchronous, half-duplex serial interface 5. control and timing logic digital considerations 1. serial interface the ltc1091/ltc1093/ltc1094 communicate with microprocessors and other external circuitry via a syn- chronous, half-duplex, 4-wire serial interface while the LTC1092 uses a 3-wire interface (see operating sequence). the clock (clk) synchronizes the data transfer with each bit being transmitted on the falling clk edge and captured on the rising clk edge in both transmitting and receiving systems. the ltc1091/ltc1093/ltc1094 first receive input data and then transmit back the a/d conversion result (half-duplex). because of the half-duplex operation, d in and d out may be tied together allowing transmission over just three wires: cs, clk and data (d in /d out ). data transfer is initiated by a falling chip select (cs) signal. after cs falls, the ltc1091/ltc1093/ltc1094 looks for a start bit. after the start bit is received, a 3-bit input word (6 bits for the ltc1093/ltc1094) is shifted into the d in input which configures the ltc1091/ltc1093/ltc1094 and starts the conversion. after one null bit, the result of the conversion is output on the d out line. at the end of the data exchange, cs should be brought high. this resets the ltc1091/ltc1093/ltc1094 in preparation for the next data exchange. the LTC1092 does not require a configuration input word and has no d in pin. a falling cs initiates data transfer as shown in the LTC1092 operating sequence. after cs falls,
12 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio d in 1 d in 2 d out 1 d out 2 cs shift mux address in 1 null bit shift a/d conversion result out 1091/2/3/4 ai01 the first clk pulse enables d out . after one null bit, the a/d conversion result is output on the d out line. bringing cs high resets the LTC1092 for the next data exchange. 2. input data word the LTC1092 requires no d in word. it is permanently configured to have a single differential input and to operate in unipolar mode. the conversion result is output on the d out line in msb-first sequence, followed by lsb-first sequence, providing easy interface to msb- or lsb-first serial ports. the following disussion applies to the con- figuration of the ltc1091/ltc1093/ltc1094. the ltc1091/ltc1093/ltc1094 clock data into the d in input on the rising edge of the clock. the input data words are defined as follows: select 1 start select 0 uni msbf mux address ltc1093/ltc1094 data input (d in )word: msb-first/ lsb-first unipolar/ bipolar 1091/2/3/4 ai02 odd/ sign sgl/ diff start msbf mux address ltc1091 data input (d in ) word: msb-first/ lsb-first odd/ sign sgl/ diff t conv t cyc t smpl hi-z filled with zeros 1091/2/3/4 ai03 clk start hi-z odd/sign msbf sgl/ diff d in d out cs b1 b9 b0 dont care t conv t cyc t smpl hi-z filled with zeros 1091/2/3/4 ai04 clk start hi-z odd/sign msbf sgl/ diff d in d out cs b1 b9 b0 b1 b9 dont care ltc1091 operating sequence example: differential inputs (ch1 + , ch0 C ) msb-first data (msbf = 1) lsb-first data (msbf = 0)
13 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio LTC1092 operating sequence t conv t cyc t smpl hi-z filled with zeros 1091/2/3/4 ai06 clk start hi-z uni sel1 sel0 msbf sgl/ diff odd/ sign d in d out cs b1 b9 b0 dont care t conv t cyc t smpl hi-z filled with zeros 1091/2/3/4 ai07 clk start hi-z hi-z uni sel1 sel0 msbf sgl/ diff odd/ sign d in d out cs b1 b9 b0 dont care b9 b1 ltc1093/ltc1094 operating sequence example: differential inputs (ch4 + , ch5 C ), unipolar mode msb-first data (msbf = 1) lsb-first data (msbf = 0) t conv t cyc t smpl t smpl 1091/2/3/4 ai05 clk hi-z d out cs b1 b9 b9 b0 b1
14 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio start bit the first logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer. the ltc1091/ltc1093/ltc1094 will ignore all leading zeros which precede this logical one. after the start bit is received, the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. multiplexer (mux) address the bits of the input word following the start bit assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following tables. in single-ended mode, all input channels are measured with respect to gnd on the ltc1091 and com on the ltc1093/ltc1094. single-ended mux mode mux address channel # gnd differential mux mode sgl/ diff 1 1 0 0 odd/ sign 0 1 0 1 0 + + 1 + + 1091-4 ai08 ltc1091 channel selection mux address select differential channel selection sgl/ diff 0 0 0 0 0 0 0 0 odd/ sign 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 + 1 + 2 + 3 + 4 + 5 + 1091-4 ai09 not used not used mux address select single-ended channel selection sgl/ diff 1 1 1 1 1 1 1 1 odd/ sign 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 + 1 + 2 + 3 + 4 + 5 + com not used not used ltc1093 channel selection mux address select differential channel selection sgl/ diff 0 0 0 0 0 0 0 0 odd/ sign 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 1091-4 ai0 mux address select single-ended channel selection sgl/ diff 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + com odd/ sign 0 0 0 0 1 1 1 1 ltc1094 channel selection
15 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio unipolar transfer curve (uni = 1) msb-first/lsb-first (msbf) the output data of the ltc1091/ltc1093/ltc1094 is programmed for msb-first or lsb-first sequence using the msbf bit. when the msbf bit is a logical one, data will appear on the d out line in msb-first format. logical zeros will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. when the msbf bit is a logical zero, lsb-first data will follow the normal msb-first data on the d out line. (see operating sequence). unipolar/bipolar (uni) the uni bit of the ltc1093/ltc1094 determines whether the conversion will be unipolar or bipolar. when uni is a logical one, a unipolar conversion will be performed on the selected input voltage. when uni is a logical zero, a bipolar conversion will result. the input span and code assign- ment for each conversion type are shown in the figures below. the ltc1091/LTC1092 are permanently configured for unipolar mode. 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1091-4 ai11 1lsb v ref ?2lsb v ref ?1lsb v ref v in 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1lsb 2lsb ? ref ? ref + 1lsb 1091-4 ai12 output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 5v) 4.9951v 4.9902v 0.0049v 0v 1091-4ai13 bipolar transfer curve (uni = 0) ltc1093/ltc1094 only unipolar output code (uni = 1) output code 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v 1lsb 2lsb ?v ref ) + 1lsb ?v ref ) input voltage (v ref = 5v) 4.9902v 4.9805v 0.0098v 0v 0.0098v 0.0195v 4.9902v 5.000v 1091-4ai14 bipolar output code (uni = 0) ltc1093/ltc1094 only
16 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio 3. accommodating microprocessors with different word lengths the ltc1091/ltc1093/ltc1094 will fill zeros indefinitely after the transmitted data until cs is brought high. at that time the d out line is disabled. this makes interfacing easy to mpu serial ports with different transfer increments including 4 bits (e.g., cop400) and 8 bits (e.g., spi and microwire/plus tm ). any word length can be accommo- dated by the correct positioning of the start bit in the ltc1091 input word. figure 1 shows examples of ltc1091 input and output words for 4-bit and 8-bit processors. a complete data exchange can be implemented with two 4-bit mpu outputs and three inputs in 4-bit systems and one 8-bit output and two inputs in 8-bit systems. the resulting data winds up left justified in the mpu with zeros automatically filled in the unused low order bits by the ltc1091. in section 5 another example is given using the mc68hc05c4 which microwire/plus is a trademark of national semiconductor corp. eliminates one 8-bit transfer and positions data right justified inside the mpu. 4. operation with d in and d out tied together the ltc1091/ltc1093/ltc1094 can be operated with d in and d out tied together. this eliminates one of the lines required to communicate to the mpu. data is transmitted in both directions on a single wire. the processor pin connected to this data line should be configurable as either an input or an output. the ltc1091, for example, will take control of the data line and drive it low on the 4th falling clk edge after the start bit is received (see figure 2). therefore, the processor port line must be switched to an input before this happens, to avoid a conflict. in the next section, an example is made of interfacing the ltc1091 with d in and d out tied together to the intel 8051 mpu. fill zeros x = don? care 1091/2/3/4 f01 clk cs d out mpu sends 2 d in words 4-bit transfers mpu reads back 3 d out words start bit d in hi-z start msbf msbf x 0 0 0 1 ? ?? b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sgl/ diff odd/ sign sgl/ diff odd/ sign msbf x sgl/ diff odd/ sign b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 start bit 0 0 0 1 mpu sends 1 d in word 8-bit transfers mpu reads back 2 d out words figure 1. ltc1091 input and output word arrangements for 4-bit and 8-bit serial port microprocessors
17 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio microwire is a trademark of national semiconductor corp. table 1. microprocessors with hardware serial interfaces compatible with the ltc1091/LTC1092/ltc1093/ltc1094 part number type of interface motorola mc6805s2, s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd63705 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous hd64180 csi/o national semiconductor cop400 family microwire tm cop800 family microwire/plus ns8050u microwire/plus hpc16000 family microwire/plus texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020 serial port *requires external hardware 5. microprocessor interfaces the ltc1091/LTC1092/ltc1093/ltc1094 can interface directly (without external hardware) to most popular microprocessor (mpu) synchronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then three or four of the mpus parallel port lines can be programmed to form the serial link to the ltc1091/ LTC1092/ltc1093/ltc1094. included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. 1091/2/3/4 f02 clk start msbf b9 b8 ? ? processor must release data line after 4th rising clk and before the 4th falling clk mpu controls data line and sends mux address to ltc1091 ltc1091 takes control of data line on 4th falling clk sgl/ diff odd/ sign cs data (d in /d out ) 12 msbf latched by ltc1091 34 ltc1091 controls data line and sends a/d result back to mpu figure 2. ltc1091 operation with d in and d out tied together
18 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio hardware and software interface to motorola mc68hc05c4 processor motorola spi (mc68hc05c4, mc68hc11) the mc68hc05c4 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfers data msb first and in 8-bit increments. with two 8-bit transfers, the a/d result is read into the mpu. the first 8-bit transfer sends the d in word to the ltc1091 and clocks b9 and b8 of the a/d conversion result into the processor. the second 8-bit transfer clocks the remaining bits, b7 through b0, into the mpu. anding the first mpu received byte with 03 hex clears the six most significant bits. notice how the position of the start bit in the first mpu transmit word is used to position the a/d result right justified in two memory locations. x = don? care 1091/2/3/4 ai15 clk cs d out mpu received word mpu transmit word start bit byte 1 d in start msbf msbf x x x b9 ? ? ? 0 b9 b8 b8 b7 b6 b5 b4 b3 b2 b1 b0 sgl/ diff odd/ sign sgl/ diff odd/ sign 0 1 byte 2 (dummy) x x x x x x x x byte 1 1st transfer ? ? byte 2 b5 b4 b3 b2 b1 b0 b7 b6 don? care 2nd transfer data exchange between ltc1091 and mc68hc05c4 1091-4 ai16 byte 1 0 0 0 0 0 0 b9 b8 d out from ltc1091 stored in mc68hc05c4 ram msb location a b7 b6 b5 b4 b3 b2 b1 b0 lsb location a + 1 byte 2 ltc1091 cs clk d in d out analog inputs co sck mosi miso mc68hc05c4 label mnemonic comments start bclrn bit 0 port c goes low (cs goes low) lda load ltc1090 d in word into acc sta load ltc1090 d in word into spi from acc transfer begins tst test status of spif bpl loop to previous instruction if not done with transfer lda load contents of spi data register into acc (d out msbs) sta start next spi cycle and clear 6 msbs of first d out word sta store in memory location a (msbs) tst test status of spif bpl loop to previous instruction if not done with transfer bsetn set b0 of port c (cs goes high) lda load contents of spi data register into acc (d out lsbs) sta store in memory location a + 1 (lsbs)
19 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio interfacing to the parallel port of the intel 8051 family the intel 8051 has been chosen to demonstrate the interface between the ltc1091 and parallel port micro- processors. normally, the cs, sclk and d in signals would be generated on three port lines and the d out signal read on a 4th port line. this works very well. however, we will demonstrate here an interface with the d in and d out of the ltc1091 tied together as described in section 4. this saves one wire. the 8051 first sends the start bit and mux address to the ltc1091 over the data line connected to p1.2. then p1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 10-bit a/d result over the same data line. 1091-4 ai17 ltc1091 cs clk d out d in analog inputs p1.4 p1.3 p1.2 8051 mux address a/d result b9 b8 b7 b6 b5 b4 b3 b2 d out from ltc1091 stored in 8051 ram msb r2 b1 b0 0 0 0 0 0 0 lsb r3 label mnemonic operand comments mov a, #ffh d in word for ltc1091 setb p1.4 make sure cs is high clr p1.4 cs goes low mov r4, #04 load counter loop 1 rlc a rotate d in bit into carry clr p1.3 sclk goes low mov p1.2, c output d in bit to ltc1091 setb p1.3 sclk goes high djnz r4, loop 1 next bit mov p1, #04 bit 2 becomes an input clr p1.3 sclk goes low mov r4, #09 load counter loop mov c, p1.2 read data bit into carry rlc a rotate data bit into acc setb p1.3 sclk goes high clr p1.3 sclk goes low djnz r4, loop next bit mov r2, a store msbs in r2 mov c, p1.2 read data bit into carry setb p1.3 sclk goes high clr p1.3 sclk goes low clr a clear acc rlc a rotate data bit from carry to acc mov c, p1.2 read data bit into carry rrc a rotate right into acc rrc a rotate right into acc mov r3, a store lsbs in r3 setb p1.4 cs goes high 1091/2/3/4 ai18 clk start msbf b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 8051 p1.2 reconfigured as an input after the 4th rising clk and before the 4th falling clk 8051 p1.2 outputs data to ltc1091 ltc1091 takes control of data line on 4th falling clk sgl/ diff odd/ sign cs data (d in /d out ) 12 msbf bit latched into ltc1091 3 4 ltc1091 sends a/d result back to 8051 p1.2
20 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio figure 3. several ltc1094s sharing one 3-wire serial interface 8 channels 8 channels 8 channels 3 3 3 3 3-wire serial interface to other peripherals or ltc1094s 2 10 output port serial data mpu ltc1091-4 f03 ltc1094 cs ltc1094 cs ltc1094 cs sharing the serial interface the ltc1094 can share the same 2- or 3-wire serial interface with other peripheral components or other ltc1094s (see figure 3). in this case, the cs signals decide which ltc1094 is being addressed by the mpu. analog considerations 1. grounding the ltc1091/LTC1092/ltc1093/ltc1094 should be used with an analog ground plane and single point grounding techniques. the agnd pin (gnd on the ltc1091/LTC1092) should be tied directly to this ground plane. the dgnd pin of the ltc1093/ltc1094 can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. the v cc pin should be bypassed to the ground plane with a 4.7 m f tantalum with leads as short as possible. av cc and dv cc should be tied together on the ltc1094. the v C pin (ltc1093/ltc1094) should be bypassed with a 0.1 m f ceramic disk. for single supply applications, v C can be tied to the ground plane. it is also recommended that the ref C pin and the com pin be tied directly to the ground plane. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. figure 4. example ground plane for the ltc1091 figure 4 shows an example of an ideal ltc1091 ground plane design for a 2-sided board. of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. because the v cc (v ref ) pin of the ltc1091 defines the voltage span of the a/d converter, its bypassing is especially important. v cc noise and ripple can be kept below 1mv by bypassing the v cc pin directly to the analog ground plane with a 4.7 m f tantalum with leads as short as possible. av cc and dv cc should be tied together on the ltc1094. figures 5 and 6 show the effects of good and poor v cc bypassing. 1 2 3 4 s s 8 7 6 5 4.7 f tantalum v cc ltc1091-4 f04
21 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio 3. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1091/ LTC1092/ltc1093/ltc1094 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. however, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to ensure that the transients caused by the current spikes settle completely before the conversion begins. source resistance the analog inputs of the ltc1091/LTC1092/ltc1093/ ltc1094 look like a 60pf capacitor (c in ) in series with a 500 w resistor (r on ) as shown in figure 7. c in gets switched between the selected + and C inputs once during each conversion cycle. large external source resis- tors and capacitances will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. + input settling this input capacitor is switched onto the + input during the sample phase (t smpl , see figure 8). the sample phase is the 1 1/2 clk cycles before the conversion starts. the voltage on the + input must settle completely within this sample time. minimizing r source + and c1 will improve the input settling time. if large + input source resistance must be used, the sample time can be increased by using a slower clk frequency. with the minimum possible sample time of 3 m s, r source + < 2k and c1 < 20pf will provide adequate settling . figure 5. poor v cc bypassing. noise and ripple can cause a/d errors 10 m s/div 1091-4 f05 0.5mv/div figure 6. good v cc bypassing keeps noise and ripple on v cc below 1mv 0.5mv/div 10 m s/div 1091-4 f06 3rd clk - r on = 500 w 4th clk c in = 60pf ltc1091 ? input r source + v in + c1 input r source v in c2 ltc091-4 f07 figure 7. analog input equivalent circuit
22 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio figure 8. + and C input settling windows C input settling at the end of the sample phase the input capacitor switches to the C input and the conversion starts (see figure 8). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage settle completely during the first clk cycle of the conversion time and be free of noise. minimizing r source C and c2 will improve settling time. if large C input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. at the maximum clk rate of 500khz, r source C < 1k w and c2 < 20pf will provide adequate settling. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 8). again, the + and C input sampling times can be extended as previously described to accommodate slower op amps. most op amps, including the lt1006 and lt1013 single supply op amps, can be made to settle well even with the minimum settling windows of 3 m s (+ input) and 2 m s (C input) which occur at the maximum clock rate of 500khz. figures 9 and 10 show examples of adequate and poor op amp settling. clk d in d out ??input ?input sample hold ??input must settle during this time t smpl t conv cs sgl/diff start msbf b9 1st bit test ?input must settle during this time 1091-4 f08 don? care
23 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio figure 10. poor op amp settling can cause a/d errors figure 9. adequate settling of op amp driving analog input 5mv/div 1 m s/div 1091-4 f09 5mv/div 20 m s/div 1091-4 f10 rc input filtering it is possible to filter the inputs with an rc network as shown in figure 11. for large values of c f (e.g., 1 m f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = (60pf)(v in /t cyc ) and is roughly proportional to v in . when running at the minimum cycle time of 32 m s, the input current equals 9 m a at v in = 5v. in this case, a filter resistor of 50 w will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increas- ing the cycle time as shown in the typical curve of maximum filter resistor vs cycle time. input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 m a (at 125 c) flowing through a source resistance of 1k w will cause a voltage drop of 1mv or 0.2lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see the typical curve of input channel leakage current vs temperature). 4. sample-and-hold single-ended inputs the ltc1091/ltc1093/ltc1094 provide a built-in sample- and-hold (s&h) function for all signals acquired in the single- ended mode. this sample-and-hold allows conversion of rapidly varying signals (see typical curve of s&h acquisition time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 8. the sampling interval begins as the bit preceding the msbf bit is shifted in and continues until the falling clk edge after the msbf bit is received. on this falling edge, the s&h goes into hold mode and the conversion begins. figure 11. rc input filtering r filter v in c filter 1091-4 f11 ltc1091 ? i dc
24 ltc1091/LTC1092 ltc1093/ltc1094 figure 12. reference input equivalent circuit u s a o pp l ic at i wu u i for atio differential inputs with differential inputs, the a/d no longer converts just a single voltage but rather the difference between two volt- ages. in this case, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the voltage on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be performed accurately. the conversion time is 10 clk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input this error would be: v error(max) = (v peak )(2 p ) ? f(C)(10/f clk ) where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. in most cases v error will not be significant. for a 60hz signal on the C input to generate a 0.25lsb error (1.25mv) with the converter running at clk = 500khz, its peak value would have to be 150mv. 5. reference inputs the voltage between the reference inputs of the ltc1091/LTC1092/ltc1093/ltc1094 defines the volt- age span of the a/d converter. the reference inputs look primarily like a 10k resistor but will have transient capaci- tive switching currents due to the switched capacitor conversion technique (see figure 12). during each bit test of the conversion (every clk cycle), a capacitive current spike will be generated on the reference pins by the a/d. these current spikes settle quickly and do not cause a problem. however, if slow settling circuitry is used to drive the reference inputs, care must be taken to ensure that transients caused by these current spikes settle com- pletely during each bit test of the conversion. when driving the reference inputs, three things should be kept in mind: 1. the source resistance (r out ) driving the reference inputs should be low (less than 1 w ) to prevent dc drops caused by the 1ma maximum reference current (i ref ). 2. transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each clk cycle). figures 13 and 14 show examples of both adequate and poor settling. using a slower clk will allow more time for the reference to settle. however, even at the maximum clk rate of 500khz most references and op amps can be made to settle within the 2 m s bit time. 3. it is recommended that the ref C input of the ltc1094 be tied directly to the analog ground plane. if ref C is biased at a voltage other than ground, the voltage must not change during a conversion cycle. this voltage must also be free of noise and ripple with respect to analog ground. r on 5pf to 30pf 10k typ ltc1091/2/3/4 ref + r out v ref every clk cycle 14 13 (agnd) 1091-4 f12 0.5mv/div 1 m s/div 1091-4 f13 figure 13. adequate reference settling
25 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i wu u i for atio 0.5mv/div 1 m s/div 1091-4 f14 figure 14. poor reference settling can cause a/d errors 6. reduced reference operation the minimum reference voltage of the ltc1091 is limited to 4.5v because the v cc supply and reference are internally tied together. however, the LTC1092/ltc1093/ltc1094 can operate with reference voltages below 1v. the effective resolution of the LTC1092/ltc1093/ltc1094 can be increased by reducing the input span of the con- verter. the parts exhibit good linearity and gain over a wide range of reference voltages (see typical curves of linearity and full-scale error vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values: 1. offset 2. noise 3. conversion speed (clk frequency) offset with reduced v ref the offset of the LTC1092/ ltc109 3/ ltc109 4 has a larger effect on the output code when the a/d is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 0.5mv which is 0.1lsb with a 5v reference becomes 0.5lsb with a 1v reference and 2.5lsbs with a 0.2v reference. if this offset is unaccept- able, it can be corrected digitally by the receiving system or by offsetting the C input to the LTC1092/ ltc109 3/ ltc109 4. noise with reduced v ref the total input-referred noise of the LTC1092/ ltc109 3/ ltc109 4 can be reduced to approximately 200 m v peak-to- peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of noise error vs reference voltage shows the lsb contribution of this 200 m v of noise. for operation with a 5v reference, the 200 m v noise is only 0.04lsb peak-to-peak. in this case, the LTC1092/ ltc109 3/ ltc109 4 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1v reference, this same 200 m v noise is 0.2lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.2lsb. if the reference is further reduced to 200mv, the 200 m v noise becomes equal to one lsb and a stable code may be difficult to achieve. in this case averaging readings may be necessary. this noise data was taken in a very clean setup. any setup- induced noise (noise or ripple on v cc , v ref , v in or v C ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. conversion speed with reduced v ref with reduced reference voltages, the lsb step size is reduced and the LTC1092/ ltc109 3/ ltc109 4 internal comparator overdrive is reduced. therefore, it may be necessary to reduce the maximum clk frequency when low values of v ref are used.
26 ltc1091/LTC1092 ltc1093/ltc1094 u s a o pp l ic at i ty p i ca l + ltc1052 56k to mcu 47 3.4k 1% 1k 0.1% 178k 0.1% 0.33 f 1 f 10 f 1091 ta03 20k 4 1 4 4 5 6 8 6 7 3 2 2 2 8 0.1 f 0.1 f cs ch0 ch1 gnd v cc clk d out d in ltc1091a 1n4148 9v 0.1 f 1 f 10k + lt1021-5 lt1025a common v in v in v out gnd j type j + 0 c to 500 c furnace exhaust gas temperature monitor with low supply detection
27 ltc1091/LTC1092 ltc1093/ltc1094 to mcu 10 f v out 1091 ta05 3 cs + gnd v cc sclk d out v ref LTC1092 lm134 or other 1 a/ k sensor 5v 4.7 f 9v 11.5k 226 lt1019-2.5 C55 c to 125 c thermometer using current output silicon sensors ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v + lt1006 1491 1091-4 ta04 10k 10% 15k 10% 5v 4.7 f ltc1094 2n3904 to mcu 4562 2954 5000 *ysi 44007, 44034 or equivalent 5k at 25 c 20 c to ?0 c * 0 c to 100 c ysi 44201 ysi 44201 0 c to 100 c 0.25 c accurate thermistor based temperature measurement system u s a o pp l ic at i ty p i ca l
28 ltc1091/LTC1092 ltc1093/ltc1094 package descriptio u dimensions in inches (millimeters) unless otherwise noted. n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 1098 0.100 (2.54) bsc 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
29 ltc1091/LTC1092 ltc1093/ltc1094 package descriptio u dimensions in inches (millimeters) unless otherwise noted. n package 16-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n16 1098 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 (2.54) bsc 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
30 ltc1091/LTC1092 ltc1093/ltc1094 n package 20-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n20 1098 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 (2.54) bsc 0.255 0.015* (6.477 0.381) 1.040* (26.416) max 12 3 4 5 6 7 8 910 19 11 12 13 14 16 15 17 18 20 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) package descriptio u dimensions in inches (millimeters) unless otherwise noted.
31 ltc1091/LTC1092 ltc1093/ltc1094 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights. package descriptio u dimensions in inches (millimeters) unless otherwise noted. s16 (wide) 1098 note 1 0.398 ?0.413* (10.109 ?10.490) 16 15 14 13 12 11 10 9 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) bsc 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** sw package 16-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620)
32 ltc1091/LTC1092 ltc1093/ltc1094 1091fa lt/tp 1099 2k rev a ? printed in usa ? linear technology corporation 1988 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments ltc1090 10-bit, 8-channel adc serial i/o, 1.5ma supply current ltc1291/ltc1292 12-bit, 2-channel and differential adcs pin compatible upgrades to ltc1091/LTC1092 ltc1293/ltc1294 12-bit, 6- and 8-channel adcs pin compatible upgrades to ltc1093/ltc1094 related parts lt1021-5 5v miso mosi c0 sck c1 10k 10k 9v isolation barrier 4n28s 51k 51k 51k 51k 300 w 5.1k 3 5v 5v 5v 5v 51k 5.1k 10k 10k 10k 10k 150 w 150 w 150 w 150 w 4n28 to additional ltc1094s nc 4n28 *solid tantalum **mc68hc05 code available from linear technology 10 f* 1 8 analog inputs 0v to 5v range to 68hc05** 10k lt1091-4 ta06 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v ltc1094 2n3906 2n3904 2n3906 + typical applicatio n u micropower, 500v optoisolated, multichannel, 10-bit data acquisition system is accessed once every two seconds

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